module gw_gao(
    \picorv32_core/riscv32_alu_u1/reg_raddr2[4] ,
    \picorv32_core/riscv32_alu_u1/reg_raddr2[3] ,
    \picorv32_core/riscv32_alu_u1/reg_raddr2[2] ,
    \picorv32_core/riscv32_alu_u1/reg_raddr2[1] ,
    \picorv32_core/riscv32_alu_u1/reg_raddr2[0] ,
    \picorv32_core/riscv32_alu_u1/reg_rdata2[31] ,
    \picorv32_core/riscv32_alu_u1/reg_rdata2[30] ,
    \picorv32_core/riscv32_alu_u1/reg_rdata2[29] ,
    \picorv32_core/riscv32_alu_u1/reg_rdata2[28] ,
    \picorv32_core/riscv32_alu_u1/reg_rdata2[27] ,
    \picorv32_core/riscv32_alu_u1/reg_rdata2[26] ,
    \picorv32_core/riscv32_alu_u1/reg_rdata2[25] ,
    \picorv32_core/riscv32_alu_u1/reg_rdata2[24] ,
    \picorv32_core/riscv32_alu_u1/reg_rdata2[23] ,
    \picorv32_core/riscv32_alu_u1/reg_rdata2[22] ,
    \picorv32_core/riscv32_alu_u1/reg_rdata2[21] ,
    \picorv32_core/riscv32_alu_u1/reg_rdata2[20] ,
    \picorv32_core/riscv32_alu_u1/reg_rdata2[19] ,
    \picorv32_core/riscv32_alu_u1/reg_rdata2[18] ,
    \picorv32_core/riscv32_alu_u1/reg_rdata2[17] ,
    \picorv32_core/riscv32_alu_u1/reg_rdata2[16] ,
    \picorv32_core/riscv32_alu_u1/reg_rdata2[15] ,
    \picorv32_core/riscv32_alu_u1/reg_rdata2[14] ,
    \picorv32_core/riscv32_alu_u1/reg_rdata2[13] ,
    \picorv32_core/riscv32_alu_u1/reg_rdata2[12] ,
    \picorv32_core/riscv32_alu_u1/reg_rdata2[11] ,
    \picorv32_core/riscv32_alu_u1/reg_rdata2[10] ,
    \picorv32_core/riscv32_alu_u1/reg_rdata2[9] ,
    \picorv32_core/riscv32_alu_u1/reg_rdata2[8] ,
    \picorv32_core/riscv32_alu_u1/reg_rdata2[7] ,
    \picorv32_core/riscv32_alu_u1/reg_rdata2[6] ,
    \picorv32_core/riscv32_alu_u1/reg_rdata2[5] ,
    \picorv32_core/riscv32_alu_u1/reg_rdata2[4] ,
    \picorv32_core/riscv32_alu_u1/reg_rdata2[3] ,
    \picorv32_core/riscv32_alu_u1/reg_rdata2[2] ,
    \picorv32_core/riscv32_alu_u1/reg_rdata2[1] ,
    \picorv32_core/riscv32_alu_u1/reg_rdata2[0] ,
    \picorv32_core/riscv32_alu_u1/jump_offset[31] ,
    \picorv32_core/riscv32_alu_u1/jump_offset[30] ,
    \picorv32_core/riscv32_alu_u1/jump_offset[29] ,
    \picorv32_core/riscv32_alu_u1/jump_offset[28] ,
    \picorv32_core/riscv32_alu_u1/jump_offset[27] ,
    \picorv32_core/riscv32_alu_u1/jump_offset[26] ,
    \picorv32_core/riscv32_alu_u1/jump_offset[25] ,
    \picorv32_core/riscv32_alu_u1/jump_offset[24] ,
    \picorv32_core/riscv32_alu_u1/jump_offset[23] ,
    \picorv32_core/riscv32_alu_u1/jump_offset[22] ,
    \picorv32_core/riscv32_alu_u1/jump_offset[21] ,
    \picorv32_core/riscv32_alu_u1/jump_offset[20] ,
    \picorv32_core/riscv32_alu_u1/jump_offset[19] ,
    \picorv32_core/riscv32_alu_u1/jump_offset[18] ,
    \picorv32_core/riscv32_alu_u1/jump_offset[17] ,
    \picorv32_core/riscv32_alu_u1/jump_offset[16] ,
    \picorv32_core/riscv32_alu_u1/jump_offset[15] ,
    \picorv32_core/riscv32_alu_u1/jump_offset[14] ,
    \picorv32_core/riscv32_alu_u1/jump_offset[13] ,
    \picorv32_core/riscv32_alu_u1/jump_offset[12] ,
    \picorv32_core/riscv32_alu_u1/jump_offset[11] ,
    \picorv32_core/riscv32_alu_u1/jump_offset[10] ,
    \picorv32_core/riscv32_alu_u1/jump_offset[9] ,
    \picorv32_core/riscv32_alu_u1/jump_offset[8] ,
    \picorv32_core/riscv32_alu_u1/jump_offset[7] ,
    \picorv32_core/riscv32_alu_u1/jump_offset[6] ,
    \picorv32_core/riscv32_alu_u1/jump_offset[5] ,
    \picorv32_core/riscv32_alu_u1/jump_offset[4] ,
    \picorv32_core/riscv32_alu_u1/jump_offset[3] ,
    \picorv32_core/riscv32_alu_u1/jump_offset[2] ,
    \picorv32_core/riscv32_alu_u1/jump_offset[1] ,
    \picorv32_core/riscv32_alu_u1/jump_offset[0] ,
    mem_valid,
    resetn,
    clk,
    tms_pad_i,
    tck_pad_i,
    tdi_pad_i,
    tdo_pad_o
);

input \picorv32_core/riscv32_alu_u1/reg_raddr2[4] ;
input \picorv32_core/riscv32_alu_u1/reg_raddr2[3] ;
input \picorv32_core/riscv32_alu_u1/reg_raddr2[2] ;
input \picorv32_core/riscv32_alu_u1/reg_raddr2[1] ;
input \picorv32_core/riscv32_alu_u1/reg_raddr2[0] ;
input \picorv32_core/riscv32_alu_u1/reg_rdata2[31] ;
input \picorv32_core/riscv32_alu_u1/reg_rdata2[30] ;
input \picorv32_core/riscv32_alu_u1/reg_rdata2[29] ;
input \picorv32_core/riscv32_alu_u1/reg_rdata2[28] ;
input \picorv32_core/riscv32_alu_u1/reg_rdata2[27] ;
input \picorv32_core/riscv32_alu_u1/reg_rdata2[26] ;
input \picorv32_core/riscv32_alu_u1/reg_rdata2[25] ;
input \picorv32_core/riscv32_alu_u1/reg_rdata2[24] ;
input \picorv32_core/riscv32_alu_u1/reg_rdata2[23] ;
input \picorv32_core/riscv32_alu_u1/reg_rdata2[22] ;
input \picorv32_core/riscv32_alu_u1/reg_rdata2[21] ;
input \picorv32_core/riscv32_alu_u1/reg_rdata2[20] ;
input \picorv32_core/riscv32_alu_u1/reg_rdata2[19] ;
input \picorv32_core/riscv32_alu_u1/reg_rdata2[18] ;
input \picorv32_core/riscv32_alu_u1/reg_rdata2[17] ;
input \picorv32_core/riscv32_alu_u1/reg_rdata2[16] ;
input \picorv32_core/riscv32_alu_u1/reg_rdata2[15] ;
input \picorv32_core/riscv32_alu_u1/reg_rdata2[14] ;
input \picorv32_core/riscv32_alu_u1/reg_rdata2[13] ;
input \picorv32_core/riscv32_alu_u1/reg_rdata2[12] ;
input \picorv32_core/riscv32_alu_u1/reg_rdata2[11] ;
input \picorv32_core/riscv32_alu_u1/reg_rdata2[10] ;
input \picorv32_core/riscv32_alu_u1/reg_rdata2[9] ;
input \picorv32_core/riscv32_alu_u1/reg_rdata2[8] ;
input \picorv32_core/riscv32_alu_u1/reg_rdata2[7] ;
input \picorv32_core/riscv32_alu_u1/reg_rdata2[6] ;
input \picorv32_core/riscv32_alu_u1/reg_rdata2[5] ;
input \picorv32_core/riscv32_alu_u1/reg_rdata2[4] ;
input \picorv32_core/riscv32_alu_u1/reg_rdata2[3] ;
input \picorv32_core/riscv32_alu_u1/reg_rdata2[2] ;
input \picorv32_core/riscv32_alu_u1/reg_rdata2[1] ;
input \picorv32_core/riscv32_alu_u1/reg_rdata2[0] ;
input \picorv32_core/riscv32_alu_u1/jump_offset[31] ;
input \picorv32_core/riscv32_alu_u1/jump_offset[30] ;
input \picorv32_core/riscv32_alu_u1/jump_offset[29] ;
input \picorv32_core/riscv32_alu_u1/jump_offset[28] ;
input \picorv32_core/riscv32_alu_u1/jump_offset[27] ;
input \picorv32_core/riscv32_alu_u1/jump_offset[26] ;
input \picorv32_core/riscv32_alu_u1/jump_offset[25] ;
input \picorv32_core/riscv32_alu_u1/jump_offset[24] ;
input \picorv32_core/riscv32_alu_u1/jump_offset[23] ;
input \picorv32_core/riscv32_alu_u1/jump_offset[22] ;
input \picorv32_core/riscv32_alu_u1/jump_offset[21] ;
input \picorv32_core/riscv32_alu_u1/jump_offset[20] ;
input \picorv32_core/riscv32_alu_u1/jump_offset[19] ;
input \picorv32_core/riscv32_alu_u1/jump_offset[18] ;
input \picorv32_core/riscv32_alu_u1/jump_offset[17] ;
input \picorv32_core/riscv32_alu_u1/jump_offset[16] ;
input \picorv32_core/riscv32_alu_u1/jump_offset[15] ;
input \picorv32_core/riscv32_alu_u1/jump_offset[14] ;
input \picorv32_core/riscv32_alu_u1/jump_offset[13] ;
input \picorv32_core/riscv32_alu_u1/jump_offset[12] ;
input \picorv32_core/riscv32_alu_u1/jump_offset[11] ;
input \picorv32_core/riscv32_alu_u1/jump_offset[10] ;
input \picorv32_core/riscv32_alu_u1/jump_offset[9] ;
input \picorv32_core/riscv32_alu_u1/jump_offset[8] ;
input \picorv32_core/riscv32_alu_u1/jump_offset[7] ;
input \picorv32_core/riscv32_alu_u1/jump_offset[6] ;
input \picorv32_core/riscv32_alu_u1/jump_offset[5] ;
input \picorv32_core/riscv32_alu_u1/jump_offset[4] ;
input \picorv32_core/riscv32_alu_u1/jump_offset[3] ;
input \picorv32_core/riscv32_alu_u1/jump_offset[2] ;
input \picorv32_core/riscv32_alu_u1/jump_offset[1] ;
input \picorv32_core/riscv32_alu_u1/jump_offset[0] ;
input mem_valid;
input resetn;
input clk;
input tms_pad_i;
input tck_pad_i;
input tdi_pad_i;
output tdo_pad_o;

wire \picorv32_core/riscv32_alu_u1/reg_raddr2[4] ;
wire \picorv32_core/riscv32_alu_u1/reg_raddr2[3] ;
wire \picorv32_core/riscv32_alu_u1/reg_raddr2[2] ;
wire \picorv32_core/riscv32_alu_u1/reg_raddr2[1] ;
wire \picorv32_core/riscv32_alu_u1/reg_raddr2[0] ;
wire \picorv32_core/riscv32_alu_u1/reg_rdata2[31] ;
wire \picorv32_core/riscv32_alu_u1/reg_rdata2[30] ;
wire \picorv32_core/riscv32_alu_u1/reg_rdata2[29] ;
wire \picorv32_core/riscv32_alu_u1/reg_rdata2[28] ;
wire \picorv32_core/riscv32_alu_u1/reg_rdata2[27] ;
wire \picorv32_core/riscv32_alu_u1/reg_rdata2[26] ;
wire \picorv32_core/riscv32_alu_u1/reg_rdata2[25] ;
wire \picorv32_core/riscv32_alu_u1/reg_rdata2[24] ;
wire \picorv32_core/riscv32_alu_u1/reg_rdata2[23] ;
wire \picorv32_core/riscv32_alu_u1/reg_rdata2[22] ;
wire \picorv32_core/riscv32_alu_u1/reg_rdata2[21] ;
wire \picorv32_core/riscv32_alu_u1/reg_rdata2[20] ;
wire \picorv32_core/riscv32_alu_u1/reg_rdata2[19] ;
wire \picorv32_core/riscv32_alu_u1/reg_rdata2[18] ;
wire \picorv32_core/riscv32_alu_u1/reg_rdata2[17] ;
wire \picorv32_core/riscv32_alu_u1/reg_rdata2[16] ;
wire \picorv32_core/riscv32_alu_u1/reg_rdata2[15] ;
wire \picorv32_core/riscv32_alu_u1/reg_rdata2[14] ;
wire \picorv32_core/riscv32_alu_u1/reg_rdata2[13] ;
wire \picorv32_core/riscv32_alu_u1/reg_rdata2[12] ;
wire \picorv32_core/riscv32_alu_u1/reg_rdata2[11] ;
wire \picorv32_core/riscv32_alu_u1/reg_rdata2[10] ;
wire \picorv32_core/riscv32_alu_u1/reg_rdata2[9] ;
wire \picorv32_core/riscv32_alu_u1/reg_rdata2[8] ;
wire \picorv32_core/riscv32_alu_u1/reg_rdata2[7] ;
wire \picorv32_core/riscv32_alu_u1/reg_rdata2[6] ;
wire \picorv32_core/riscv32_alu_u1/reg_rdata2[5] ;
wire \picorv32_core/riscv32_alu_u1/reg_rdata2[4] ;
wire \picorv32_core/riscv32_alu_u1/reg_rdata2[3] ;
wire \picorv32_core/riscv32_alu_u1/reg_rdata2[2] ;
wire \picorv32_core/riscv32_alu_u1/reg_rdata2[1] ;
wire \picorv32_core/riscv32_alu_u1/reg_rdata2[0] ;
wire \picorv32_core/riscv32_alu_u1/jump_offset[31] ;
wire \picorv32_core/riscv32_alu_u1/jump_offset[30] ;
wire \picorv32_core/riscv32_alu_u1/jump_offset[29] ;
wire \picorv32_core/riscv32_alu_u1/jump_offset[28] ;
wire \picorv32_core/riscv32_alu_u1/jump_offset[27] ;
wire \picorv32_core/riscv32_alu_u1/jump_offset[26] ;
wire \picorv32_core/riscv32_alu_u1/jump_offset[25] ;
wire \picorv32_core/riscv32_alu_u1/jump_offset[24] ;
wire \picorv32_core/riscv32_alu_u1/jump_offset[23] ;
wire \picorv32_core/riscv32_alu_u1/jump_offset[22] ;
wire \picorv32_core/riscv32_alu_u1/jump_offset[21] ;
wire \picorv32_core/riscv32_alu_u1/jump_offset[20] ;
wire \picorv32_core/riscv32_alu_u1/jump_offset[19] ;
wire \picorv32_core/riscv32_alu_u1/jump_offset[18] ;
wire \picorv32_core/riscv32_alu_u1/jump_offset[17] ;
wire \picorv32_core/riscv32_alu_u1/jump_offset[16] ;
wire \picorv32_core/riscv32_alu_u1/jump_offset[15] ;
wire \picorv32_core/riscv32_alu_u1/jump_offset[14] ;
wire \picorv32_core/riscv32_alu_u1/jump_offset[13] ;
wire \picorv32_core/riscv32_alu_u1/jump_offset[12] ;
wire \picorv32_core/riscv32_alu_u1/jump_offset[11] ;
wire \picorv32_core/riscv32_alu_u1/jump_offset[10] ;
wire \picorv32_core/riscv32_alu_u1/jump_offset[9] ;
wire \picorv32_core/riscv32_alu_u1/jump_offset[8] ;
wire \picorv32_core/riscv32_alu_u1/jump_offset[7] ;
wire \picorv32_core/riscv32_alu_u1/jump_offset[6] ;
wire \picorv32_core/riscv32_alu_u1/jump_offset[5] ;
wire \picorv32_core/riscv32_alu_u1/jump_offset[4] ;
wire \picorv32_core/riscv32_alu_u1/jump_offset[3] ;
wire \picorv32_core/riscv32_alu_u1/jump_offset[2] ;
wire \picorv32_core/riscv32_alu_u1/jump_offset[1] ;
wire \picorv32_core/riscv32_alu_u1/jump_offset[0] ;
wire mem_valid;
wire resetn;
wire clk;
wire tms_pad_i;
wire tck_pad_i;
wire tdi_pad_i;
wire tdo_pad_o;
wire tms_i_c;
wire tck_i_c;
wire tdi_i_c;
wire tdo_o_c;
wire [9:0] control0;
wire gao_jtag_tck;
wire gao_jtag_reset;
wire run_test_idle_er1;
wire run_test_idle_er2;
wire shift_dr_capture_dr;
wire update_dr;
wire pause_dr;
wire enable_er1;
wire enable_er2;
wire gao_jtag_tdi;
wire tdo_er1;

IBUF tms_ibuf (
    .I(tms_pad_i),
    .O(tms_i_c)
);

IBUF tck_ibuf (
    .I(tck_pad_i),
    .O(tck_i_c)
);

IBUF tdi_ibuf (
    .I(tdi_pad_i),
    .O(tdi_i_c)
);

OBUF tdo_obuf (
    .I(tdo_o_c),
    .O(tdo_pad_o)
);

GW_JTAG  u_gw_jtag(
    .tms_pad_i(tms_i_c),
    .tck_pad_i(tck_i_c),
    .tdi_pad_i(tdi_i_c),
    .tdo_pad_o(tdo_o_c),
    .tck_o(gao_jtag_tck),
    .test_logic_reset_o(gao_jtag_reset),
    .run_test_idle_er1_o(run_test_idle_er1),
    .run_test_idle_er2_o(run_test_idle_er2),
    .shift_dr_capture_dr_o(shift_dr_capture_dr),
    .update_dr_o(update_dr),
    .pause_dr_o(pause_dr),
    .enable_er1_o(enable_er1),
    .enable_er2_o(enable_er2),
    .tdi_o(gao_jtag_tdi),
    .tdo_er1_i(tdo_er1),
    .tdo_er2_i(1'b0)
);

gw_con_top  u_icon_top(
    .tck_i(gao_jtag_tck),
    .tdi_i(gao_jtag_tdi),
    .tdo_o(tdo_er1),
    .rst_i(gao_jtag_reset),
    .control0(control0[9:0]),
    .enable_i(enable_er1),
    .shift_dr_capture_dr_i(shift_dr_capture_dr),
    .update_dr_i(update_dr)
);

ao_top_0  u_la0_top(
    .control(control0[9:0]),
    .trig0_i(resetn),
    .data_i({\picorv32_core/riscv32_alu_u1/reg_raddr2[4] ,\picorv32_core/riscv32_alu_u1/reg_raddr2[3] ,\picorv32_core/riscv32_alu_u1/reg_raddr2[2] ,\picorv32_core/riscv32_alu_u1/reg_raddr2[1] ,\picorv32_core/riscv32_alu_u1/reg_raddr2[0] ,\picorv32_core/riscv32_alu_u1/reg_rdata2[31] ,\picorv32_core/riscv32_alu_u1/reg_rdata2[30] ,\picorv32_core/riscv32_alu_u1/reg_rdata2[29] ,\picorv32_core/riscv32_alu_u1/reg_rdata2[28] ,\picorv32_core/riscv32_alu_u1/reg_rdata2[27] ,\picorv32_core/riscv32_alu_u1/reg_rdata2[26] ,\picorv32_core/riscv32_alu_u1/reg_rdata2[25] ,\picorv32_core/riscv32_alu_u1/reg_rdata2[24] ,\picorv32_core/riscv32_alu_u1/reg_rdata2[23] ,\picorv32_core/riscv32_alu_u1/reg_rdata2[22] ,\picorv32_core/riscv32_alu_u1/reg_rdata2[21] ,\picorv32_core/riscv32_alu_u1/reg_rdata2[20] ,\picorv32_core/riscv32_alu_u1/reg_rdata2[19] ,\picorv32_core/riscv32_alu_u1/reg_rdata2[18] ,\picorv32_core/riscv32_alu_u1/reg_rdata2[17] ,\picorv32_core/riscv32_alu_u1/reg_rdata2[16] ,\picorv32_core/riscv32_alu_u1/reg_rdata2[15] ,\picorv32_core/riscv32_alu_u1/reg_rdata2[14] ,\picorv32_core/riscv32_alu_u1/reg_rdata2[13] ,\picorv32_core/riscv32_alu_u1/reg_rdata2[12] ,\picorv32_core/riscv32_alu_u1/reg_rdata2[11] ,\picorv32_core/riscv32_alu_u1/reg_rdata2[10] ,\picorv32_core/riscv32_alu_u1/reg_rdata2[9] ,\picorv32_core/riscv32_alu_u1/reg_rdata2[8] ,\picorv32_core/riscv32_alu_u1/reg_rdata2[7] ,\picorv32_core/riscv32_alu_u1/reg_rdata2[6] ,\picorv32_core/riscv32_alu_u1/reg_rdata2[5] ,\picorv32_core/riscv32_alu_u1/reg_rdata2[4] ,\picorv32_core/riscv32_alu_u1/reg_rdata2[3] ,\picorv32_core/riscv32_alu_u1/reg_rdata2[2] ,\picorv32_core/riscv32_alu_u1/reg_rdata2[1] ,\picorv32_core/riscv32_alu_u1/reg_rdata2[0] ,\picorv32_core/riscv32_alu_u1/jump_offset[31] ,\picorv32_core/riscv32_alu_u1/jump_offset[30] ,\picorv32_core/riscv32_alu_u1/jump_offset[29] ,\picorv32_core/riscv32_alu_u1/jump_offset[28] ,\picorv32_core/riscv32_alu_u1/jump_offset[27] ,\picorv32_core/riscv32_alu_u1/jump_offset[26] ,\picorv32_core/riscv32_alu_u1/jump_offset[25] ,\picorv32_core/riscv32_alu_u1/jump_offset[24] ,\picorv32_core/riscv32_alu_u1/jump_offset[23] ,\picorv32_core/riscv32_alu_u1/jump_offset[22] ,\picorv32_core/riscv32_alu_u1/jump_offset[21] ,\picorv32_core/riscv32_alu_u1/jump_offset[20] ,\picorv32_core/riscv32_alu_u1/jump_offset[19] ,\picorv32_core/riscv32_alu_u1/jump_offset[18] ,\picorv32_core/riscv32_alu_u1/jump_offset[17] ,\picorv32_core/riscv32_alu_u1/jump_offset[16] ,\picorv32_core/riscv32_alu_u1/jump_offset[15] ,\picorv32_core/riscv32_alu_u1/jump_offset[14] ,\picorv32_core/riscv32_alu_u1/jump_offset[13] ,\picorv32_core/riscv32_alu_u1/jump_offset[12] ,\picorv32_core/riscv32_alu_u1/jump_offset[11] ,\picorv32_core/riscv32_alu_u1/jump_offset[10] ,\picorv32_core/riscv32_alu_u1/jump_offset[9] ,\picorv32_core/riscv32_alu_u1/jump_offset[8] ,\picorv32_core/riscv32_alu_u1/jump_offset[7] ,\picorv32_core/riscv32_alu_u1/jump_offset[6] ,\picorv32_core/riscv32_alu_u1/jump_offset[5] ,\picorv32_core/riscv32_alu_u1/jump_offset[4] ,\picorv32_core/riscv32_alu_u1/jump_offset[3] ,\picorv32_core/riscv32_alu_u1/jump_offset[2] ,\picorv32_core/riscv32_alu_u1/jump_offset[1] ,\picorv32_core/riscv32_alu_u1/jump_offset[0] ,mem_valid}),
    .clk_i(clk)
);

endmodule
